The development of the storage class memory (SCM) devices have blurred the boundaries between storage (slow, cheap, and non-volatile) and memory (fast, expensive, and volatile) in the computer and semiconductor industry. Metal oxide multi-level cell (MLC) memories are one of the most promising candidates to achieve all the SCM features, such as non-volatile, short access times, low cost per bit, and solid state requirements. The SCM cells are often compared on the basis of a measure term F2, or “feature size squared”. The smaller the F2 measure, the more SCM cells per unit area. In a three-dimensional (3D) vertical memory array architecture, resistance random access memories (RRAM) made of metal oxide resistor elements may be able to achieve 0.5 F2 with an eight-layer stack. An eight-layer stack may introduce severe integration challenges with the technology node scaled down. However, four levels of multi-level-cell (MLC) operation helps to achieve the same F2 measure with half the number of the memory cell layers. As a well known factor, the metal oxide memory cells have been operated at the breakdown region. Minimum endurance requirements in the solid-state storage device application for MLC memories are much smaller than for single level cell (SLC) memories with the technology node scaled down.